杜源

通信工程系 博导

个人简历

杜源,副教授,博士生导师,国家级青年人才计划获得者,IEEE高级会员,中国电子学会(CIE)高级会员,中国计算机学会(CCF)高级会员。现任IEEE标准协会专用领域加速器(DSA)方向专家组成员、超大规模集成电路及应用(VSA)技术委员会委员,中国计算机学会(CCF)集成电路设计专委、容错计算专委执行委员等。本科毕业于东南大学吴健雄学院(强化班)信息工程专业,硕士、博士均毕业于美国加州大学洛杉矶分校(UCLA),博士期间师从美国国家工程院院士张懋中(M.C. Frank Chang) 教授,先后承担多项美国权威机构资助课题,获得博通(Broadcom)青年学者基金。博士毕业后,作为美国耐能公司(Kneron)创始团队成员,完成业内首款面向智能家居物联网的人工智能芯片量产,2019年回国加入港澳宝典资料大全。

现阶段主要从事高速芯片互联(光/电IO,SerDes,CDR等)、异构计算(光电融合、存内计算、专用领域加速器等)以及智能感知算法编译部署方面的科研工作。在IEEE权威期刊及行业顶级会议上发表论文60余篇,包括JSSC,ISSCC,VLSI,TCAS-I/II,TVLSI,TCAD,TMTT,MWTL,CVPR,ICCV,ICML等高水平国际期刊和会议,并获IEEE Circuits and Systems Society(电路与系统学会)达林顿(Darlington)2021年度最佳期刊论文奖,2023 IEEE国际专用集成电路会议(ASICON)最佳论文奖,2023 IEEE集成电路与微系统国际会议(ICICM)最佳论文奖。智能类脑计算芯片方面的研究入选省科协评选的“2022年度江苏省行业领域(电子信息领域)十大科技进展”。

现主持国家重点研发计划青年科学家项目,国家自然科学基金国际(地区)合作与交流项目、青年项目,教育部联合基金项目,江苏省自然科学基金青年项目,中国计算机学会(CCF)-蚂蚁科研基金项目等。先后入选海外国家级青年人才(2019)、华为“紫金学者” (2020)、江苏省“双创人才” (2021)、江苏省“双创团队”领军人才(2023)等。

在教学与学生培养方面,共同开设《高级模拟集成电路设计与实践课程》,获全国高校电子信息类专业课程实验教学案例设计竞赛全国二等奖。指导学生获互联网+竞赛全国金奖,集成电路EDA设计精英挑战赛全国一等奖,中国大学生集成电路创新创业大赛全国二等奖,江苏省优秀毕业论文二等奖,港澳宝典资料大全优秀毕业论文特等奖,港澳宝典资料大全栋梁奖学金等多项荣誉。

课题组现在开放招收博士、硕士研究生,招聘专职科研人员和博士后,诚邀有志于共同探索高速互联、异构计算、智能感知算法等研究方向的同学以及海内外学者加盟,更多研究方向信息请点击

研究方向

高速互联芯片设计:Chiplet芯粒间/存储器与加速器间/传感器与加速器间高速互联,光互连,时钟数据恢复(CDR),有线/无线高速SerDes Transceiver等;

异构计算芯片设计:专用领域AI加速芯片,光电融合计算、存内计算芯片;

主要课程

1. 《高级模拟与射频集成电路设计与实践》

2. 《大语言模型在芯片设计中的应用与实践》

3. 《集成电路专业导学课》

代表成果

1.高速互联:

[1.1]Q. Liu, L. Du and Y. Du, A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects, in IEEE Journal of Solid-State Circuits, vol. 58, no. 8, pp. 2326-2336,Aug. 2023

[1.2]Y. Du, et.al, A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection, in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1111-1122, April 2017 [IEEE Xplore][PDF]

[1.3]Y. Kim et al., A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications, in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1600-1612, June 2019

[1.4]J. Du, et.al, A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface, 2020 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2020, pp. 1-2

[1.5]Y. Wu, T. Li, Z. Shao, L. Du and Y. Du, An Efficient Design Framework for 2×2 CNN Accelerator Chiplet Cluster with SerDes Interconnects, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-5


2.异构计算

[2.1]L. Du, et.al, A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 1, pp. 198-208, Jan. 2018(IEEE CAS Dalington Best Paper, 2021)[IEEE Xplore][PDF]

[2.2]Z. Shao et al., Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 2, pp. 668-681, Feb. 2022 [IEEE Xplore] [PDF]

[2.3]L. Du, et.al, A Reconfigurable 64-Dimension K-Means Clustering Accelerator with Adaptive Overflow Control, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 4, pp. 760-764, Apr. 2020

[2.4]Y. Bai et al., An Efficient High-Throughput Structured-Light Depth Engine, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 8, pp. 1047-1058, Aug. 2022

[2.5]C. Xie, Z. Shao, Z. Chen, Y. Du and L. Du, An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. , no. 01, pp. 1-5, 5555, Dec.2023

[2.6] Y. Du, et al., Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications, in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 7, no. 1, pp. 10-17, June 2021 [IEEE Xplore][PDF]

[2.7] Y. Du, et al., An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT), in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 10, pp. 1811-1819, Oct. 2019 [IEEE Xplore][PDF]


3.传感算法及物联网系统

[3.1]H. Shui, et.al, A Low-Power High-Accuracy Urban Waterlogging Depth Sensor Based on Millimeter-Wave FMCW Radar. Sensors 2022, 22, 1236

[3.2]Y. Mei, et.al, A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security, 2020 33rd IEEE International System-on-Chip Conference (SOCC), Sep, 2020

[3.3]X.Zhang, Z.Cheng, L. Du, Y. Du, Progressive Classifier Mechanism for Bridge Expansion Joint Health Status Monitoring System Based on Acoustic Sensors. Sensors 2023, 23, 5090

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